Ettus Research LLC

02/17/2012

03:10 am fpga Revision 2ad9e0ad: dsp_engine: fix for upper/lower swap, and odd length packets

03:10 am uhd Revision 2ad9e0ad: dsp_engine: fix for upper/lower swap, and odd length packets

02/03/2012

04:59 am uhd Revision ae1997f8: power_trig: test code for power trigger

04:59 am fpga Revision ae1997f8: power_trig: test code for power trigger

01:57 am fpga Revision 1ce83a07: power_trig: first cut at power trigger with fixed delay

02/02/2012

07:00 pm fpga Revision 17f5776c: dsp_rework: testbench enhancements

02/01/2012

01:22 am fpga Revision 7b69532a: dsp_rework: handle longer headers

01/31/2012

08:06 pm fpga Revision 08b60ada: dsp_rework: more thorough test

12:35 am fpga Revision 9803334f: dsp_engine: work with transport header

01/30/2012

07:09 am fpga Revision ac35b413: dsp: 8 to 16 bit conversion for tx side. believed to be functional