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//
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// Copyright 2011 Ettus Research LLC
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.
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//
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module rssi (input clock, input reset, input enable,
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	     input [11:0] adc, output [15:0] rssi, output [15:0] over_count);
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   wire 		  over_hi = (adc == 12'h7FF);
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   wire 		  over_lo = (adc == 12'h800);
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   wire 		  over = over_hi | over_lo;
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   reg [25:0] 		  over_count_int;
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   always @(posedge clock)
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     if(reset | ~enable)
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       over_count_int <= #1 26'd0;
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     else
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       over_count_int <= #1 over_count_int + (over ? 26'd65535 : 26'd0) - over_count_int[25:10];
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   assign      over_count = over_count_int[25:10];
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   wire [11:0] abs_adc = adc[11] ? ~adc : adc;
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   reg [25:0]  rssi_int;
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   always @(posedge clock)
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     if(reset | ~enable)
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       rssi_int <= #1 26'd0;
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     else
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       rssi_int <= #1 rssi_int + abs_adc - rssi_int[25:10];
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   assign      rssi = rssi_int[25:10];
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endmodule // rssi