root / fpga / README.txt @ master
History | View | Annotate | Download (2.5 KB)
| 1 |
######################################################################## |
|---|---|
| 2 |
## Welcome to the USRP FPGA source code tree |
| 3 |
######################################################################## |
| 4 |
|
| 5 |
usrp1/ |
| 6 |
|
| 7 |
Description: generation 1 products |
| 8 |
|
| 9 |
Devices: USRP classic only |
| 10 |
|
| 11 |
Tools: Quartus from Altera |
| 12 |
|
| 13 |
Project file: usrp1/toplevel/usrp_std/ |
| 14 |
|
| 15 |
usrp2/ |
| 16 |
|
| 17 |
Description: generation 2 products |
| 18 |
|
| 19 |
Devices: USRP2, N2XX, B100, E1XX |
| 20 |
|
| 21 |
Tools: ISE from Xilinx, GNU make |
| 22 |
|
| 23 |
Build Instructions: |
| 24 |
1) ensure that xtclsh is in the $PATH |
| 25 |
2) cd usrp2/top/<project-directory> |
| 26 |
3) make -f Makefile.<device> bin |
| 27 |
4) bin file in build-<device>/*.bin |
| 28 |
|
| 29 |
######################################################################## |
| 30 |
## Customizing the DSP |
| 31 |
######################################################################## |
| 32 |
|
| 33 |
As part of the USRP FPGA build-framework, |
| 34 |
there are several convenient places for users to insert |
| 35 |
custom DSP modules into the transmit and receive chains. |
| 36 |
|
| 37 |
* before the DDC module |
| 38 |
* after the DDC module |
| 39 |
* replace the DDC module |
| 40 |
* before the DUC module |
| 41 |
* after the DUC module |
| 42 |
* replace of the DUC module |
| 43 |
* as an RX packet engine |
| 44 |
* as an TX packet engine |
| 45 |
|
| 46 |
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 47 |
Customizing the top level makefile |
| 48 |
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 49 |
Each USRP device has a makefile associated with it. |
| 50 |
This makefile contains all of the necessary build rules. |
| 51 |
When making a customized FPGA design, |
| 52 |
start by copying the current makefile for your device. |
| 53 |
Makefiles can be found in the usrp2/top/<dir>/Makefile.* |
| 54 |
|
| 55 |
Edit your new makefile: |
| 56 |
* set BUILD_DIR to a unique directory name |
| 57 |
* set CUSTOM_SRCS for your verilog sources |
| 58 |
* set CUSTOM_DEFS (see section below) |
| 59 |
|
| 60 |
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 61 |
Inserting custom modules |
| 62 |
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ |
| 63 |
CUSTOM_DEFS is a string of space-separate key-value pairs. |
| 64 |
Set the CUSTOM_DEFS variable so the FPGA fabric glue |
| 65 |
will substitute your custom modules into the DSP chain. |
| 66 |
|
| 67 |
Example: |
| 68 |
CUSTOM_DEFS = "TX_ENG0_MODULE=my_tx_engine RX_ENG0_MODULE=my_rx_engine" |
| 69 |
Where my_tx_engine and my_rx_engine are the names of custom verilog modules. |
| 70 |
|
| 71 |
The following module definition keys are possible (X is a DSP number): |
| 72 |
|
| 73 |
* TX_ENG<X>_MODULE: set the module for the transmit chain engine. |
| 74 |
* RX_ENG<X>_MODULE: set the module for the receive chain engine. |
| 75 |
* RX_DSP<X>_MODULE: set the module for the transmit dsp chain. |
| 76 |
* TX_DSP<X>_MODULE: set the module for the receive dsp chain. |
| 77 |
|
| 78 |
Examples of custom modules can be found in usrp2/custom/*.v |