Revision f139c98a
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# |
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# Copyright 2011 Ettus Research LLC |
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# |
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all: B100 |
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find -name "*.twr" | xargs grep constraint | grep met |
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clean: |
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rm -rf build* |
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B100: |
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make -f Makefile.$@ bin |
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.PHONY: all clean |
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## Main Clock |
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NET "CLK_FPGA_P" LOC = "R7" ; |
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NET "CLK_FPGA_N" LOC = "T7" ; |
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## UART |
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NET "FPGA_TXD" LOC = "H16" ; |
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NET "FPGA_RXD" LOC = "H12" ; |
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## I2C |
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NET "SDA_FPGA" LOC = "T13" ; |
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NET "SCL_FPGA" LOC = "R13" ; |
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## CGEN |
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NET "cgen_st_ld" LOC = "M13" ; |
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NET "cgen_st_refmon" LOC = "J14" ; |
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NET "cgen_st_status" LOC = "P6" ; |
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NET "cgen_ref_sel" LOC = "T2" ; |
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NET "cgen_sync_b" LOC = "H15" ; |
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## FPGA Config |
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#NET "fpga_cfg_din" LOC = "T14" ; |
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#NET "fpga_cfg_cclk" LOC = "R14" ; |
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#NET "fpga_cfg_init_b" LOC = "T12" ; |
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## MISC |
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#NET "mystery_bus<2>" LOC = "T11" ; |
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#NET "mystery_bus<1>" LOC = "C4" ; |
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#NET "mystery_bus<0>" LOC = "E7" ; |
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NET "reset_n" LOC = "D5" ; |
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NET "PPS_IN" LOC = "M14" ; |
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NET "reset_codec" LOC = "B14" ; |
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## GPIF |
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NET "GPIF_D<15>" LOC = "P7" ; |
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NET "GPIF_D<14>" LOC = "N8" ; |
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NET "GPIF_D<13>" LOC = "T5" ; |
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NET "GPIF_D<12>" LOC = "T6" ; |
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NET "GPIF_D<11>" LOC = "N6" ; |
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NET "GPIF_D<10>" LOC = "P5" ; |
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NET "GPIF_D<9>" LOC = "R3" ; |
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NET "GPIF_D<8>" LOC = "T3" ; |
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NET "GPIF_D<7>" LOC = "N12" ; |
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NET "GPIF_D<6>" LOC = "P13" ; |
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NET "GPIF_D<5>" LOC = "P11" ; |
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NET "GPIF_D<4>" LOC = "R9" ; |
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NET "GPIF_D<3>" LOC = "T9" ; |
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NET "GPIF_D<2>" LOC = "N9" ; |
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NET "GPIF_D<1>" LOC = "P9" ; |
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NET "GPIF_D<0>" LOC = "P8" ; |
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NET "GPIF_CTL<3>" LOC = "N5" ; |
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NET "GPIF_CTL<2>" LOC = "M11" ; |
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NET "GPIF_CTL<1>" LOC = "M9" ; |
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NET "GPIF_CTL<0>" LOC = "M7" ; |
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NET "GPIF_RDY<3>" LOC = "N11" ; |
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NET "GPIF_RDY<2>" LOC = "T10" ; |
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NET "GPIF_RDY<1>" LOC = "T4" ; |
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NET "GPIF_RDY<0>" LOC = "R5" ; |
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NET "FX2_PA7_FLAGD" LOC = "P12" ; |
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NET "FX2_PA6_PKTEND" LOC = "R11" ; |
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NET "FX2_PA2_SLOE" LOC = "P10" ; |
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NET "IFCLK" LOC = "T8" ; |
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## LEDs |
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NET "debug_led<2>" LOC = "R2" ; |
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NET "debug_led<1>" LOC = "N4" ; |
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NET "debug_led<0>" LOC = "P4" ; |
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## Debug bus |
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NET "debug_clk<0>" LOC = "K15" ; |
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NET "debug_clk<1>" LOC = "K14" ; |
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NET "debug<0>" LOC = "K16" ; |
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NET "debug<1>" LOC = "J16" ; |
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NET "debug<2>" LOC = "C16" ; |
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NET "debug<3>" LOC = "C15" ; |
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NET "debug<4>" LOC = "E13" ; |
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NET "debug<5>" LOC = "D14" ; |
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NET "debug<6>" LOC = "D16" ; |
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NET "debug<7>" LOC = "D15" ; |
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NET "debug<8>" LOC = "E14" ; |
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NET "debug<9>" LOC = "F13" ; |
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NET "debug<10>" LOC = "G13" ; |
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NET "debug<11>" LOC = "F14" ; |
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NET "debug<12>" LOC = "E16" ; |
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NET "debug<13>" LOC = "F15" ; |
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NET "debug<14>" LOC = "H13" ; |
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NET "debug<15>" LOC = "G14" ; |
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NET "debug<16>" LOC = "G16" ; |
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NET "debug<17>" LOC = "F16" ; |
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NET "debug<18>" LOC = "J12" ; |
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NET "debug<19>" LOC = "J13" ; |
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NET "debug<20>" LOC = "L14" ; |
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NET "debug<21>" LOC = "L16" ; |
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NET "debug<22>" LOC = "M15" ; |
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NET "debug<23>" LOC = "M16" ; |
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NET "debug<24>" LOC = "L13" ; |
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NET "debug<25>" LOC = "K13" ; |
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NET "debug<26>" LOC = "P16" ; |
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NET "debug<27>" LOC = "N16" ; |
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NET "debug<28>" LOC = "R15" ; |
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NET "debug<29>" LOC = "P15" ; |
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NET "debug<30>" LOC = "N13" ; |
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NET "debug<31>" LOC = "N14" ; |
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## ADC |
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NET "adc<11>" LOC = "B15" ; |
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NET "adc<10>" LOC = "A8" ; |
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NET "adc<9>" LOC = "B8" ; |
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NET "adc<8>" LOC = "C8" ; |
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NET "adc<7>" LOC = "D8" ; |
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NET "adc<6>" LOC = "C9" ; |
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NET "adc<5>" LOC = "A9" ; |
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NET "adc<4>" LOC = "C10" ; |
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NET "adc<3>" LOC = "D9" ; |
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NET "adc<2>" LOC = "A3" ; |
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NET "adc<1>" LOC = "B3" ; |
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NET "adc<0>" LOC = "A4" ; |
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NET "RXSYNC" LOC = "D10" ; |
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## DAC |
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NET "TXBLANK" LOC = "K1" ; |
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NET "TXSYNC" LOC = "J2" ; |
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NET "dac<0>" LOC = "J1" ; |
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NET "dac<1>" LOC = "H3" ; |
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NET "dac<2>" LOC = "J3" ; |
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NET "dac<3>" LOC = "G2" ; |
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NET "dac<4>" LOC = "H1" ; |
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NET "dac<5>" LOC = "N3" ; |
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NET "dac<6>" LOC = "M4" ; |
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NET "dac<7>" LOC = "R1" ; |
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NET "dac<8>" LOC = "P2" ; |
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NET "dac<9>" LOC = "P1" ; |
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NET "dac<10>" LOC = "M1" ; |
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NET "dac<11>" LOC = "N1" ; |
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NET "dac<12>" LOC = "M3" ; |
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NET "dac<13>" LOC = "L4" ; |
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## TX DB |
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NET "io_tx<0>" LOC = "K4" ; |
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NET "io_tx<1>" LOC = "L3" ; |
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NET "io_tx<2>" LOC = "L2" ; |
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NET "io_tx<3>" LOC = "F1" ; |
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NET "io_tx<4>" LOC = "F3" ; |
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NET "io_tx<5>" LOC = "G3" ; |
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NET "io_tx<6>" LOC = "E3" ; |
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NET "io_tx<7>" LOC = "E2" ; |
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NET "io_tx<8>" LOC = "E4" ; |
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NET "io_tx<9>" LOC = "F4" ; |
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NET "io_tx<10>" LOC = "D1" ; |
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NET "io_tx<11>" LOC = "E1" ; |
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NET "io_tx<12>" LOC = "D4" ; |
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NET "io_tx<13>" LOC = "D3" ; |
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NET "io_tx<14>" LOC = "C2" ; |
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NET "io_tx<15>" LOC = "C1" ; |
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## RX DB |
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NET "io_rx<0>" LOC = "D7" ; |
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NET "io_rx<1>" LOC = "C6" ; |
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NET "io_rx<2>" LOC = "A6" ; |
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NET "io_rx<3>" LOC = "B6" ; |
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NET "io_rx<4>" LOC = "E9" ; |
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NET "io_rx<5>" LOC = "A7" ; |
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NET "io_rx<6>" LOC = "C7" ; |
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NET "io_rx<7>" LOC = "B10" ; |
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NET "io_rx<8>" LOC = "A10" ; |
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NET "io_rx<9>" LOC = "C11" ; |
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NET "io_rx<10>" LOC = "A11" ; |
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NET "io_rx<11>" LOC = "D11" ; |
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NET "io_rx<12>" LOC = "B12" ; |
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NET "io_rx<13>" LOC = "A12" ; |
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NET "io_rx<14>" LOC = "A14" ; |
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NET "io_rx<15>" LOC = "A13" ; |
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## SPI |
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#NET "SEN_AUX" LOC = "C12" ; |
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#NET "SCLK_AUX" LOC = "D12" ; |
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#NET "MISO_AUX" LOC = "J5" ; |
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NET "SCLK_CODEC" LOC = "K3" ; |
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NET "SEN_CODEC" LOC = "D13" ; |
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NET "MOSI_CODEC" LOC = "C13" ; |
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NET "MISO_CODEC" LOC = "G4" ; |
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NET "MISO_RX_DB" LOC = "E6" ; |
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NET "SEN_RX_DB" LOC = "B4" ; |
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NET "MOSI_RX_DB" LOC = "A5" ; |
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NET "SCLK_RX_DB" LOC = "C5" ; |
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NET "MISO_TX_DB" LOC = "J4" ; |
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NET "SEN_TX_DB" LOC = "N2" ; |
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NET "MOSI_TX_DB" LOC = "L1" ; |
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NET "SCLK_TX_DB" LOC = "G1" ; |
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## Dedicated pins |
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#NET "TMS" LOC = "B2" ; |
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#NET "TDO" LOC = "B16" ; |
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#NET "TDI" LOC = "B1" ; |
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#NET "TCK" LOC = "A15" ; |
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#NET "fpga_cfg_prog_b" LOC = "A2" ; |
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#NET "fpga_cfg_done" LOC = "T15" ; |
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// |
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// Copyright 2011 Ettus Research LLC |
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// |
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// This program is free software: you can redistribute it and/or modify |
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// it under the terms of the GNU General Public License as published by |
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// the Free Software Foundation, either version 3 of the License, or |
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// (at your option) any later version. |
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// |
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// This program is distributed in the hope that it will be useful, |
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// but WITHOUT ANY WARRANTY; without even the implied warranty of |
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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// GNU General Public License for more details. |
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// |
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// You should have received a copy of the GNU General Public License |
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// along with this program. If not, see <http://www.gnu.org/licenses/>. |
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// |
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`timescale 1ns / 1ps |
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////////////////////////////////////////////////////////////////////////////////// |
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module u1plus |
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(input CLK_FPGA_P, input CLK_FPGA_N, // Diff |
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output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk, |
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output FPGA_TXD, input FPGA_RXD, |
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// GPIF |
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inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY, |
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output FX2_PA7_FLAGD, output FX2_PA6_PKTEND, output FX2_PA2_SLOE, |
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input IFCLK, |
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inout SDA_FPGA, inout SCL_FPGA, // I2C |
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output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB, // DB TX SPI |
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output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB, // DB TX SPI |
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output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC, // AD9862 main SPI |
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input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, |
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inout [15:0] io_tx, inout [15:0] io_rx, |
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output [13:0] dac, output TXSYNC, output TXBLANK, |
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input [11:0] adc, input RXSYNC, |
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input PPS_IN, |
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input reset_n, output reset_codec |
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); |
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assign reset_codec = 1; // Believed to be active low |
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// ///////////////////////////////////////////////////////////////////////// |
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// Clocking |
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wire clk_fpga, clk_fpga_in, reset; |
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IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE"))
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clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N)); |
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BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga)); |
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reset_sync reset_sync(.clk(clk_fpga), .reset_in(~reset_n), .reset_out(reset)); |
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// ///////////////////////////////////////////////////////////////////////// |
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// SPI |
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wire mosi, sclk, miso; |
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assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0;
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assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0;
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assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0;
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assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) | |
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(~SEN_CODEC & MISO_CODEC); |
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// ///////////////////////////////////////////////////////////////////////// |
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// TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL |
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assign TXBLANK = 0; |
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wire [13:0] tx_i, tx_q; |
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genvar i; |
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generate |
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for(i=0;i<14;i=i+1) |
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begin : gen_dacout |
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ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
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.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 |
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.SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
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ODDR2_inst (.Q(dac[i]), // 1-bit DDR output data |
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.C0(clk_fpga), // 1-bit clock input |
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.C1(~clk_fpga), // 1-bit clock input |
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.CE(1'b1), // 1-bit clock enable input |
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.D0(tx_i[i]), // 1-bit data input (associated with C0) |
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.D1(tx_q[i]), // 1-bit data input (associated with C1) |
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.R(1'b0), // 1-bit reset input |
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.S(1'b0)); // 1-bit set input |
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end // block: gen_dacout |
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endgenerate |
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ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
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.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1 |
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.SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
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ODDR2_txsnc (.Q(TXSYNC), // 1-bit DDR output data |
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.C0(clk_fpga), // 1-bit clock input |
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.C1(~clk_fpga), // 1-bit clock input |
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.CE(1'b1), // 1-bit clock enable input |
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.D0(1'b0), // 1-bit data input (associated with C0) |
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.D1(1'b1), // 1-bit data input (associated with C1) |
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.R(1'b0), // 1-bit reset input |
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.S(1'b0)); // 1-bit set input |
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// ///////////////////////////////////////////////////////////////////////// |
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// RX ADC -- handles deinterleaving |
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reg [11:0] rx_i, rx_q; |
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wire [11:0] rx_a, rx_b; |
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genvar j; |
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generate |
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for(j=0;j<12;j=j+1) |
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begin : gen_adcin |
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IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
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.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 |
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.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 |
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.SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
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IDDR2_inst (.Q0(rx_a[j]), // 1-bit output captured with C0 clock |
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.Q1(rx_b[j]), // 1-bit output captured with C1 clock |
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.C0(clk_fpga), // 1-bit clock input |
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.C1(~clk_fpga), // 1-bit clock input |
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.CE(1'b1), // 1-bit clock enable input |
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.D(adc[j]), // 1-bit DDR data input |
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.R(1'b0), // 1-bit reset input |
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.S(1'b0)); // 1-bit set input |
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end // block: gen_adcin |
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endgenerate |
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IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
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| 131 |
.INIT_Q0(1'b0), // Sets initial state of the Q0 output to 1’b0 or 1’b1 |
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| 132 |
.INIT_Q1(1'b0), // Sets initial state of the Q1 output to 1’b0 or 1’b1 |
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| 133 |
.SRTYPE("SYNC")) // Specifies "SYNC" or "ASYNC" set/reset
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| 134 |
IDDR2_sync (.Q0(rxsync_0), // 1-bit output captured with C0 clock |
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| 135 |
.Q1(rxsync_1), // 1-bit output captured with C1 clock |
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| 136 |
.C0(clk_fpga), // 1-bit clock input |
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| 137 |
.C1(~clk_fpga), // 1-bit clock input |
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| 138 |
.CE(1'b1), // 1-bit clock enable input |
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| 139 |
.D(RXSYNC), // 1-bit DDR data input |
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| 140 |
.R(1'b0), // 1-bit reset input |
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| 141 |
.S(1'b0)); // 1-bit set input |
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| 142 |
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| 143 |
always @(posedge clk_fpga) |
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| 144 |
if(rxsync_0) |
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| 145 |
begin |
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| 146 |
rx_i <= rx_b; |
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| 147 |
rx_q <= rx_a; |
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| 148 |
end |
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| 149 |
else |
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| 150 |
begin |
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| 151 |
rx_i <= rx_a; |
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| 152 |
rx_q <= rx_b; |
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| 153 |
end |
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| 154 |
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| 155 |
// ///////////////////////////////////////////////////////////////////////// |
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| 156 |
// Main U1E Core |
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| 157 |
u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset), |
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| 158 |
.debug_led(debug_led), .debug(debug), .debug_clk(debug_clk), |
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| 159 |
.debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD), |
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| 160 |
.gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY), |
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| 161 |
.gpif_misc({FX2_PA7_FLAGD,FX2_PA6_PKTEND,FX2_PA2_SLOE}),
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| 162 |
.gpif_clk(IFCLK), |
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| 163 |
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| 164 |
.db_sda(SDA_FPGA), .db_scl(SCL_FPGA), |
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| 165 |
.sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso),
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| 166 |
.cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), |
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| 167 |
.cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel), |
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| 168 |
.io_tx(io_tx), .io_rx(io_rx), |
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| 169 |
.tx_i(tx_i), .tx_q(tx_q), |
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| 170 |
.rx_i(rx_i), .rx_q(rx_q), |
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| 171 |
.pps_in(PPS_IN) ); |
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| 172 |
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| 173 |
endmodule // u1plus |
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Also available in: Unified diff