uhd

     else if(src_rdy_i & dst_rdy_o) begin //valid read

        VITA_PAYLOAD : begin

            //step through each element until line done, then reset

            vector_phase <= (line_done)? 0: vector_phase + 1;

            //decrement the packet count after each line

            pkt_len <= (line_done)? pkt_len - 1 : pkt_len;

            //end of frame reached, determine next state

            //otherwise, keep processing through the payload

            if (line_done && vita_eof) begin

                if (eof) begin

                    vita_state <= (USE_TRANS_HEADER==1) ? VITA_TRANS_HEADER : VITA_HEADER;

                end

                else if (has_trailer_reg) begin

                    vita_state <= VITA_TRAILER;

                end

                else begin

                    vita_state <= VITA_DUMP;

                end

            end //line_done && vita_eof

        end //end VITA_PAYLOAD

     end //valid read

   //sample registers for de-framing a vector input

   reg [31:0] sample_reg [1:0];

     if(src_rdy_i && dst_rdy_o)

        sample_reg[vector_phase] <= data_i[31:0];

   wire store = (vita_state == VITA_PAYLOAD)? (src_rdy_i && line_done) : 0;

   assign dst_rdy_o = (vita_state == VITA_PAYLOAD)? fifo_space : 1;

    //assign registered/live data to the samples vector

    //the numchan'th sample vector is muxed to live data

    wire [(32*MAXCHAN)-1:0] samples;

    generate

    genvar i;

    for (i=0; i < MAXCHAN; i = i +1) begin : assign_samples

        wire live_data = (i == (MAXCHAN-1))? 1 : numchan == i;

        assign samples[32*i + 31:32*i] = (live_data)? data_i[31:0] : sample_reg[i];

    end

    endgenerate

   assign fifo_i = {samples,seqnum_err,has_tics_reg,is_sob_reg,is_eob_reg,eop,