Revision b6dae16e
| b/host/lib/usrp/usrp2/clock_ctrl.cpp | ||
|---|---|---|
| 212 | 212 |
std::vector<double> get_rates_tx_dboard_clock(void){
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| 213 | 213 |
return get_rates_rx_dboard_clock(); //same master clock, same dividers... |
| 214 | 214 |
} |
| 215 |
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void enable_test_clock(bool enb) {
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_ad9510_regs.power_down_lvpecl_out0 = enb? |
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ad9510_regs_t::POWER_DOWN_LVPECL_OUT0_NORMAL : |
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ad9510_regs_t::POWER_DOWN_LVPECL_OUT0_SAFE_PD; |
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_ad9510_regs.output_level_lvpecl_out0 = ad9510_regs_t::OUTPUT_LEVEL_LVPECL_OUT0_810MV; |
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_ad9510_regs.divider_low_cycles_out0 = 0; |
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_ad9510_regs.divider_high_cycles_out0 = 0; |
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_ad9510_regs.bypass_divider_out0 = 1; |
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this->write_reg(0x3c); |
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this->write_reg(0x48); |
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this->write_reg(0x49); |
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} |
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| 215 | 228 |
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/*! |
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* If we are to use an external reference, enable the charge pump. |
| b/host/lib/usrp/usrp2/clock_ctrl.hpp | ||
|---|---|---|
| 83 | 83 |
* \param enb true to enable |
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*/ |
| 85 | 85 |
virtual void enable_external_ref(bool enb) = 0; |
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/*! |
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* Enable/disable test clock output. |
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* \param enb true to enable |
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*/ |
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virtual void enable_test_clock(bool enb) = 0; |
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| 86 | 92 |
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| 87 | 93 |
/*! |
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* TODO other clock control api here.... |
| b/host/lib/usrp/usrp2/mboard_impl.cpp | ||
|---|---|---|
| 168 | 168 |
default: throw std::runtime_error("usrp2: unhandled clock configuration reference source");
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} |
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} else {
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switch(_clock_config.ref_source){
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| 173 | 172 |
case clock_config_t::REF_INT : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x10); break; |
| 174 | 173 |
case clock_config_t::REF_SMA : _iface->poke32(_iface->regs.misc_ctrl_clock, 0x1C); break; |
| ... | ... | |
| 178 | 177 |
} |
| 179 | 178 |
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//clock source ref 10mhz |
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bool use_external = _clock_config.ref_source != clock_config_t::REF_INT; |
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bool use_external = (_clock_config.ref_source != clock_config_t::REF_INT) |
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|| (_iface->get_hw_rev() >= USRP2P_FIRST_HW_REV); //USRP2P has an internal 10MHz TCXO |
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_clock_ctrl->enable_external_ref(use_external); |
| 183 | 183 |
} |
| 184 | 184 |
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| b/host/utils/usrp2p_fw_update.py | ||
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| 40 | 40 |
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| 41 | 41 |
#from bootloader_utils.h |
| 42 | 42 |
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#define FPGA_IMAGE_SIZE_BYTES 1572864
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#define FW_IMAGE_SIZE_BYTES 31744
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#define SAFE_FPGA_IMAGE_LOCATION_ADDR 0x00000000
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#define SAFE_FW_IMAGE_LOCATION_ADDR 0x003F0000
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#define PROD_FPGA_IMAGE_LOCATION_ADDR 0x00180000
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#define PROD_FW_IMAGE_LOCATION_ADDR 0x00300000
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FPGA_IMAGE_SIZE_BYTES = 1572864
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FW_IMAGE_SIZE_BYTES = 31744
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SAFE_FPGA_IMAGE_LOCATION_ADDR = 0x00000000
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SAFE_FW_IMAGE_LOCATION_ADDR = 0x003F0000
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PROD_FPGA_IMAGE_LOCATION_ADDR = 0x00180000
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PROD_FW_IMAGE_LOCATION_ADDR = 0x00300000
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| 49 | 49 |
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| 50 | 50 |
FLASH_DATA_PACKET_SIZE = 256 |
| 51 | 51 |
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