root / usrp2 / gpmc / gpmc.v @ b115e4d7
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`timescale 1ns / 1ps |
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////////////////////////////////////////////////////////////////////////////////// |
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module gpmc |
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(input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE, |
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input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE, |
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input wb_clk, input wb_rst, |
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output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso, |
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output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i |
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); |
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wire EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6)); |
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wire [15:0] EM_D_ram; |
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reg [15:0] EM_D_wb; |
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assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb; |
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// CS4 is RAM_2PORT for high-speed data |
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ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port |
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(.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram), |
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.clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob()); |
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// CS6 is Control, Wishbone bus bridge (wb master) |
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// Sync version |
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reg [1:0] cs_del, we_del, oe_del; |
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// Synchronize the async control signals |
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always @(posedge wb_clk) |
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begin |
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cs_del <= { cs_del[0], EM_NCS6 };
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we_del <= { we_del[0], EM_NWE };
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oe_del <= { oe_del[0], EM_NOE };
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end |
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always @(posedge wb_clk) |
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if(cs_del == 2'b10) // Falling Edge |
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wb_adr_o <= { EM_A, 1'b0 };
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always @(posedge wb_clk) |
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if(we_del == 2'b10) // Falling Edge |
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begin |
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wb_dat_mosi <= EM_D; |
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wb_sel_o <= ~EM_NBE; |
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end |
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always @(posedge wb_clk) |
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if(wb_ack_i) |
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EM_D_wb <= wb_dat_miso; |
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// stb, oe_del, we_del |
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assign wb_cyc_o = wb_stb_o; |
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always @(posedge wb_clk) |
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if( ~cs_del[0] & (we_del == 2'b10) ) |
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wb_we_o <= 1; |
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else if(wb_ack_i) // Turn off we when done. Could also use we_del[0], others... |
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wb_we_o <= 0; |
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always @(posedge wb_clk) |
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if( ~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10))) |
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wb_stb_o <= 1; |
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else if(wb_ack_i) |
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wb_stb_o <= 0; |
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endmodule // gpmc |