Revision b115e4d7 usrp2/top/u1e/u1e.v

b/usrp2/top/u1e/u1e.v
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//////////////////////////////////////////////////////////////////////////////////
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module u1e
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  (
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   input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
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  (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
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   output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
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   // GPMC
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   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A,
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   input EM_WAIT0, input EM_NCS4, input EM_NWP, input EM_NWE, input EM_NOE, input EM_NADV_ALE
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   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,
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   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE
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   );
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   // FPGA-specific pins connections
......
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   IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
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   clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
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   // Debug circuitry
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   reg [31:0] 	ctr;
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   always @(posedge clk_fpga)
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     ctr <= ctr + 1;
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   assign debug_led = ctr[27:25];
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   assign debug_clk = { EM_CLK, clk_fpga };
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   assign debug = { { EM_WAIT0, EM_NADV_ALE, EM_NWP, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },
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		    { EM_D } };
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   wire 	EM_output_enable = (~EM_NOE & ~EM_NCS4);
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   wire [15:0] 	EM_D_out;
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   assign EM_D = EM_output_enable ? EM_D_out : 16'bz;
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   ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port
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     (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_out),
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      .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob());
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   u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
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		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
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		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
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		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
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endmodule // u2plus
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endmodule // u1e

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