uhd

*~

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

module gpmc

  (input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,

   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE,

   input wb_clk, input wb_rst,

   output reg [10:0] wb_adr_o, output reg [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,

   output reg [1:0] wb_sel_o, output wb_cyc_o, output reg wb_stb_o, output reg wb_we_o, input wb_ack_i

   );

   wire 	EM_output_enable = (~EM_NOE & (~EM_NCS4 | ~EM_NCS6));

   wire [15:0] 	EM_D_ram;

   reg [15:0] 	EM_D_wb;

   assign EM_D = ~EM_output_enable ? 16'bz : ~EM_NCS4 ? EM_D_ram : EM_D_wb;

   // CS4 is RAM_2PORT for high-speed data

   ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port

     (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram),

      .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob());

   // CS6 is Control, Wishbone bus bridge (wb master)

   // Sync version

   reg [1:0] 	cs_del, we_del, oe_del;

   // Synchronize the async control signals

   always @(posedge wb_clk)

     begin

	cs_del <= { cs_del[0], EM_NCS6 };

	we_del <= { we_del[0], EM_NWE };

	oe_del <= { oe_del[0], EM_NOE };

     end

   always @(posedge wb_clk)

     if(cs_del == 2'b10)  // Falling Edge

       wb_adr_o <= { EM_A, 1'b0 };

   always @(posedge wb_clk)

     if(we_del == 2'b10)  // Falling Edge

       begin

	  wb_dat_mosi <= EM_D;

	  wb_sel_o <= ~EM_NBE;

       end

   always @(posedge wb_clk)

     if(wb_ack_i)

       EM_D_wb <= wb_dat_miso;

   // stb, oe_del, we_del

   assign wb_cyc_o = wb_stb_o;

   always @(posedge wb_clk)

     if( ~cs_del[0] & (we_del == 2'b10) )

       wb_we_o <= 1;

     else if(wb_ack_i)  // Turn off we when done.  Could also use we_del[0], others...

       wb_we_o <= 0;

   always @(posedge wb_clk)

     if( ~cs_del[0] & ((we_del == 2'b10) | (oe_del == 2'b10)))

       wb_stb_o <= 1;

     else if(wb_ack_i)

       wb_stb_o <= 0;

endmodule // gpmc

gpmc/gpmc.v \

top/u1e/u1e_core.v \

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

module tb_u1e();

   wire [2:0] debug_led;

   wire [31:0] debug;

   wire [1:0] debug_clk;

   // GPMC

   wire       EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;

   wire [15:0] EM_D;

   wire [10:1] EM_A;

   wire [1:0]  EM_NBE;

   reg  clk_fpga = 0;

   always #100 clk_fpga = ~clk_fpga;

   u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),

		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),

		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 

		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );

endmodule // u1e

NET "EM_NCS6"  LOC = "E17"  ;

NET "EM_CLK"  LOC = "F11"  ;

NET "EM_NBE<1>"  LOC = "D14"  ;

NET "EM_NBE<0>"  LOC = "A13"  ;

#NET "EM_NADV_ALE"  LOC = "B15"  ;

#NET "EM_NWP"  LOC = "F13"  ;

  (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff

   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,

   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE

   u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),

		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),

		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 

		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );

endmodule // u1e

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

module u1e_core

  (input clk_fpga, output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,

   // GPMC

   input EM_CLK, inout [15:0] EM_D, input [10:1] EM_A, input [1:0] EM_NBE,

   input EM_WAIT0, input EM_NCS4, input EM_NCS6, input EM_NWE, input EM_NOE

   );

   // Debug circuitry

   reg [31:0] 	ctr;

   always @(posedge clk_fpga)

     ctr <= ctr + 1;

   assign debug_led = ctr[27:25];

   assign debug_clk = { EM_CLK, clk_fpga };

   assign debug = { { 1'b0, EM_WAIT0, EM_NCS6, EM_NCS4, EM_NWE, EM_NOE, EM_A[10:1] },

		    { EM_D } };

   wire 	wb_clk, wb_rst;

   wire 	wb_cyc, wb_stb, wb_we, wb_ack;

   wire [1:0] 	wb_sel;

   wire [10:0] 	wb_adr;

   wire [15:0] 	wb_dat_mosi, wb_dat_miso;

   gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),

	      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE), 

	      .EM_NOE(EM_NOE),

	      .wb_clk(wb_clk), .wb_rst(wb_rst),

	      .wb_adr_o(wb_adr), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso),

	      .wb_sel_o(wb_sel), .wb_cyc_o(wb_cyc), .wb_stb_o(wb_stb), .wb_we_o(wb_we),

	      .wb_ack_i(wb_ack));

   assign wb_clk = clk_fpga;

   reg [15:0] 	reg_fast, reg_slow;

   localparam [10:0] WB_ADR_REG_FAST = 36;

   localparam [10:0] WB_ADR_REG_SLOW = 38;

   always @(posedge wb_clk)

     if(wb_cyc & wb_stb & wb_we & (wb_adr == WB_ADR_REG_FAST))

       reg_fast <= wb_dat_mosi;

   assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx;

   assign wb_ack = wb_stb & wb_cyc;

endmodule // u2plus