Revision 0a28cb5e
| ID | 0a28cb5e7fbe81009e50fe03c4ffc3ce8db5052a |
Added to DCM's and some BUFG's to align the internal 125MHz clock edge with its presentation externally at the NoBL SRAM.
Since we don't have a board level trace to use to estimate clock propigation delay we just loop through the I/O on the FPGA.
This hasn't been verified as working on a USRP2 yet.
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